IBM has announced the development of a new 5nm manufacturing process, based on 'nanosheets, ' which it claims offers considerable advantages over existing FinFET technology. To create 5 nm chips, the company is ditching the standard FinFET architecture in favor of a new structure built with a stack of four nanosheets, allowing some 30 billion transistors to be packed onto a chip the size of a fingernail and promising significant gains in power and efficiency.
The team reported the resulting increase in performance should help accelerate cognitive computing, IoT, and other data-intensive applications delivered in the cloud; the power savings could also mean that the batteries in smartphones and other mobile products could last two to three times longer than today's devices, before needing to be charged.
The innovation at the core of the new chip is a brand-new architecture, eschewing the current FinFET (fin field effect) design in favor of stacks of silicon nanosheets.
The transistors are built with Extreme Ultraviolet (EUV) lithography, which is used to stencil the circuit designs on chips. If you wanted to optimize for power savings, alternatively, you could create chips with the same performance level as todays 10nm units, but with a 75 percent reduction in how much power is needed to achieve that performance. This fine-tuning of performance versus power tradeoffs is impossible for FinFETs, which are constrained by their fin height, rendering them unable to increase current flow for higher performance when scaled to 5nm, according to the researchers.
"We put the entire process together, measure, validate and then our partners get full access to the technology to take it from proof point with us at IBM to manufacturing", said Khare.
As promising as the technical merits may be here, however, we can not forget the economic considerations of Moore's law, said McGregor, which will likely leave semiconductor makers like GlobalFoundries looking to leverage the FinFET technology for as long as possible to recoup the major investments that it and its partners have made. In the past, a similarly sized chip would hold 20 billion transistors at most.
Scientists have been saying with more frequency that Moore's Law may be at, or at least near, its outer limits due to the limitations of physical science. More details about its 5nm process will be revealed at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan, which is happening this week.
IBM's newest process was discovered by its Research Alliance which includes Samsung and GlobalFoundries. We shouldn't expect 7nm any time before 2018 at the earliest, so 5nm is still quite a while away.